Reductions in the size and inherent features of semiconductor devices (e.g., metal-oxide-semiconductor (MOS) devices) have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and a drain of a MOS device alters a resistance associated with the channel region, thereby affecting the performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming all other parameters are maintained relatively constant, may allow an increase in current flow between the source and the drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of MOS devices, stress may be introduced into the channel region of a MOS device to improve its carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in a source-to-drain direction.
A commonly used method for applying compressive stresses to the channel regions of PMOS devices is to grow SiGe stressors in source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate; forming spacers on sidewalls of the gate stack; forming recesses in the silicon substrate along the gate spacers; epitaxially growing SiGe stressors in the recesses; and then annealing. SiGe stressors apply a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor. Similarly, for NMOS devices, stressors that may introduce tensile stresses, such as SiC stressors, may be formed.
The conventional stressor formation processes suffer drawbacks, however. Although the epitaxially grown SiGe stressors have the ability of applying high stresses to the channel regions, the subsequent source/drain implantation of impurities adversely causes the relaxation of the stresses. It has been found that after the subsequent implantation and the rapid thermal annealing, the channel stress may be reduced from about 1.7 GPa to about 0.9 GPa, or even less. Even worse, the relaxation of the stresses is more significant in SiGe stressors having high stresses, which are incurred by a high concentration of germanium.
An additional problem lies in the increase of leakage currents. During the impurity implantation, silicon and germanium atoms are dislocated from lattice locations. The subsequent rapid thermal anneal causes the propagation of the dislocations toward source/drain junctions, and hence higher leakage currents.
Accordingly, what is needed in the art are MOS devices that incorporate stressors thereof to take advantage of the benefits associated with increased channel stresses while at the same time overcoming the deficiencies of the prior art.